The 1T1C DRAM Cell

Prerequisites(1)

Builds on to(2)

Dynamic Random-Access Memory (DRAM) stores each bit using just one transistor and one capacitor (1T1C), making it the densest form of semiconductor memory. This density comes at a cost: the stored charge leaks away, so every cell must be refreshed periodically.

How a DRAM Cell Stores Data

The single capacitor holds a charge representing the stored bit:

Capacitor State	Logic Value
Charged (above threshold)	1
Discharged (below threshold)	0

The single NMOS access transistor connects the capacitor to the bit line, gated by the word line. When the word line is LOW, the transistor is OFF and the capacitor is isolated, slowly leaking charge through junction leakage currents.

Destructive Read

Reading a DRAM cell is destructive. Here is the sequence:

Precharge the bit line to VDD/2 (midpoint voltage).
Assert the word line -- the access transistor turns ON, connecting the capacitor to the bit line.
The capacitor shares its charge with the (much larger) bit line capacitance, causing a tiny voltage deviation on the bit line -- positive if the cell stored a 1, negative if it stored a 0.
A sense amplifier detects this deviation and drives the bit line fully to VDD or GND.
This amplified voltage rewrites the cell, restoring the charge that was disturbed. This is the "write-back" or restore phase.

Without the restore phase, every read would drain the capacitor and destroy the stored data.

Refresh Requirement

Even without reads, charge leaks away through the transistor's sub-threshold leakage. The industry-standard refresh interval is approximately 64 ms -- every cell in the entire DRAM must be read and rewritten within this window. The memory controller schedules REF commands that cycle through all rows. Refresh consumes bandwidth and power, and becomes a bigger burden as DRAM density increases.

DRAM Array Organization

DRAM cells are arranged in a 2D grid of rows and columns:

Term	Definition
Row (word line)	Activating one word line connects an entire row of cells to their bit lines
Column	Selected by the column address after the row is opened
Row buffer	The sense amplifiers hold the entire activated row -- subsequent reads to the same row are fast (row hit)
Bank	An independent sub-array with its own row buffer; multiple banks allow concurrent operations
Rank	A group of banks (chips) that share a command/address bus and operate in lockstep

DDR Generations

Double Data Rate (DDR) DRAM transfers data on both clock edges. Each generation increases prefetch width and bus speed:

Generation	Data Rate (MT/s)	Prefetch	Voltage
DDR3	800 - 2133	8n	1.5 V
DDR4	2133 - 3200	8n	1.2 V
DDR5	4800 - 8400+	16n	1.1 V

DDR5 also introduced on-die ECC and doubled the bank count per chip, improving both reliability and parallelism.

**Dynamic Random-Access Memory (DRAM)** stores each bit using just **one transistor and one capacitor (1T1C)**, making it the densest form of semiconductor memory. This density comes at a cost: the stored charge leaks away, so every cell must be **refreshed** periodically.

### How a DRAM Cell Stores Data

The single **capacitor** holds a charge representing the stored bit:

| Capacitor State | Logic Value |
|----------------|-------------|
| Charged (above threshold) | **1** |
| Discharged (below threshold) | **0** |

The single **NMOS access transistor** connects the capacitor to the **bit line**, gated by the **word line**. When the word line is LOW, the transistor is OFF and the capacitor is isolated, slowly leaking charge through junction leakage currents.

### Destructive Read

Reading a DRAM cell is **destructive**. Here is the sequence:

1. **Precharge** the bit line to VDD/2 (midpoint voltage).
2. **Assert the word line** -- the access transistor turns ON, connecting the capacitor to the bit line.
3. The capacitor shares its charge with the (much larger) bit line capacitance, causing a **tiny voltage deviation** on the bit line -- positive if the cell stored a 1, negative if it stored a 0.
4. A **sense amplifier** detects this deviation and drives the bit line fully to VDD or GND.
5. This amplified voltage **rewrites** the cell, restoring the charge that was disturbed. This is the "write-back" or **restore** phase.

Without the restore phase, every read would drain the capacitor and destroy the stored data.

### Refresh Requirement

Even without reads, charge leaks away through the transistor's sub-threshold leakage. The industry-standard refresh interval is approximately **64 ms** -- every cell in the entire DRAM must be read and rewritten within this window. The memory controller schedules **REF commands** that cycle through all rows. Refresh consumes **bandwidth** and **power**, and becomes a bigger burden as DRAM density increases.

### DRAM Array Organization

DRAM cells are arranged in a 2D grid of **rows** and **columns**:

| Term | Definition |
|------|-----------|
| **Row (word line)** | Activating one word line connects an entire row of cells to their bit lines |
| **Column** | Selected by the column address after the row is opened |
| **Row buffer** | The sense amplifiers hold the entire activated row -- subsequent reads to the same row are fast (**row hit**) |
| **Bank** | An independent sub-array with its own row buffer; multiple banks allow concurrent operations |
| **Rank** | A group of banks (chips) that share a command/address bus and operate in lockstep |

### DDR Generations

**Double Data Rate (DDR)** DRAM transfers data on both clock edges. Each generation increases prefetch width and bus speed:

| Generation | Data Rate (MT/s) | Prefetch | Voltage |
|-----------|------------------|----------|---------|
| DDR3 | 800 - 2133 | 8n | 1.5 V |
| DDR4 | 2133 - 3200 | 8n | 1.2 V |
| DDR5 | 4800 - 8400+ | 16n | 1.1 V |

DDR5 also introduced **on-die ECC** and doubled the bank count per chip, improving both reliability and parallelism.

Real-Life: A Leaky Bucket That Needs Refilling

Real-World Example

Think of a DRAM cell as a small bucket with a tiny leak. To store a "1", you fill the bucket with water. Over time the water slowly drains out through the leak. Before it empties completely, someone must come by and refill it -- that is the refresh operation. To store a "0", you keep the bucket empty (no water to leak).

Reading the bucket is destructive: you pour its contents into a measuring cup to check the level. Now the bucket is empty regardless of what it stored, so you must pour the water back (the restore/write-back step).

Practical applications and real-world context:

Main system memory: Every laptop, phone, and server uses DRAM for its primary working memory. A typical desktop has 16-64 GB of DDR5, containing hundreds of billions of 1T1C cells.
Row buffer locality: When a program accesses memory addresses within the same DRAM row, they are served from the already-opened row buffer at near-SRAM speed (~15 ns). Accessing a different row requires a precharge + activate sequence (~40-50 ns). Database engines and OS schedulers exploit this by grouping related data into the same row.
Refresh overhead: In a 16 Gb DRAM chip with 64K rows, refresh must cycle through all rows every 64 ms -- about one row per microsecond. During refresh, the bank is unavailable. At high densities, refresh can consume 10-20% of available bandwidth.
DRAM vs SRAM tradeoff: DRAM is ~6x denser (1T1C vs 6T) and ~10x cheaper per bit, but 50-100x slower. This is why computers use a memory hierarchy: small fast SRAM caches backed by large cheap DRAM main memory.
Server ECC DRAM: Servers use ECC DIMMs that detect and correct single-bit errors (from cosmic rays, alpha particles, or charge leakage). DDR5 adds an additional on-die ECC layer inside each chip.

DRAM Cell and Array Organization

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