Back to DAG

Transistor

hardware

MOSFET: The Digital Switch

A transistor is a semiconductor device that acts as a voltage-controlled switch. In modern digital circuits, the dominant type is the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). Every processor, memory chip, and digital IC is built from billions of MOSFETs.

Two Types of MOSFET

There are two complementary types:

  • NMOS (N-channel MOSFET): conducts (switch ON) when the gate voltage is HIGH (logic 1). When the gate is low, the channel between drain and source is closed — no current flows.
  • PMOS (P-channel MOSFET): conducts (switch ON) when the gate voltage is LOW (logic 0). When the gate is high, the channel is closed. PMOS is drawn with a bubble on the gate to indicate inversion.

Each MOSFET has three terminals:

  1. Gate (G): the control input — voltage here determines whether the switch is on or off.
  2. Drain (D): where current flows in from (NMOS) or out to (PMOS).
  3. Source (S): where current flows out to (NMOS) or in from (PMOS). In NMOS the source connects to ground (GND); in PMOS the source connects to supply voltage (VDD).

Threshold Voltage

A MOSFET does not switch instantaneously. The threshold voltage (Vth) is the minimum gate-to-source voltage needed to turn the transistor on. Below Vth, the transistor is off; above it, the transistor conducts. Modern transistors have Vth values around 0.2-0.5V.

Encoding Binary with Voltage

Digital circuits use two voltage ranges to represent binary:

  • Logic 1 (HIGH): voltage close to VDD (e.g., 1.0V in modern chips)
  • Logic 0 (LOW): voltage close to GND (0V)

The transistor acts as a restoring switch — it pulls the output firmly to VDD or GND, preventing signal degradation as logic propagates through layers of gates.

CMOS: Complementary MOS

CMOS (Complementary MOS) pairs an NMOS and a PMOS transistor together. This is the foundation of all modern logic:

  • The PMOS network (pull-up) connects the output to VDD.
  • The NMOS network (pull-down) connects the output to GND.
  • They are complementary: when one network conducts, the other is off. This means no static current flows between VDD and GND, which is why CMOS is extremely power-efficient.

The simplest CMOS circuit is the inverter (NOT gate): a single PMOS on top and a single NMOS on the bottom. When input is HIGH, the NMOS conducts (pulls output to GND = 0) and PMOS is off. When input is LOW, the PMOS conducts (pulls output to VDD = 1) and NMOS is off.

Why Transistors Matter

  • A modern CPU contains billions of transistors (Apple M2: ~20 billion; NVIDIA H100: ~80 billion)
  • Moore's Law observes that transistor count doubles roughly every two years
  • Smaller transistors = faster switching + lower power + more logic per chip
  • Current leading-edge: 3nm process nodes with gate lengths under 10 nanometers

Real-Life: Light Switch Analogy

Real-World Example

Think of a transistor as an electrically controlled light switch. A regular wall switch needs your finger to flip it — a transistor uses a voltage signal on the gate instead.

  • NMOS is like a normally-off switch: apply voltage to the gate and the circuit connects (light turns on). Remove the gate voltage and it disconnects.
  • PMOS is like a normally-on switch: apply voltage to the gate and the circuit disconnects (light turns off). Remove the gate voltage and it connects.

The CMOS inverter is like having two switches in series: one connected to the power supply (PMOS) and one to ground (NMOS). Exactly one is always closed, so the output is always driven — never floating.

In real hardware:

  • Processors: billions of CMOS transistors implement all arithmetic, control, and memory logic
  • SRAM cache: each bit is stored using 6 transistors in a cross-coupled configuration
  • DRAM: each bit uses just 1 transistor + 1 capacitor, enabling very dense memory
  • Flash storage (SSD): floating-gate transistors trap electrons to store data even without power

NMOS, PMOS, and CMOS Inverter

NMOS Transistor G D S ON when Gate=HIGH PMOS Transistor G S VDD D ON when Gate=LOW CMOS Inverter (NOT gate) VDD PMOS OUT NMOS GND IN Inverter Truth Table IN OUT 0 1 1 0
Step 1 of 2