From Transistors to Logic Gates
A logic gate is a physical circuit built from transistors that implements a Boolean function. While boolean logic defines the abstract operations and transistors provide the switching mechanism, logic gates are the bridge between them — the fundamental building blocks of all digital hardware.
Building Gates from CMOS Transistors
Each CMOS logic gate has two networks of transistors:
- Pull-up network (PMOS): connects output to VDD (logic 1)
- Pull-down network (NMOS): connects output to GND (logic 0)
The two networks are duals of each other: where one uses series connections, the other uses parallel, and vice versa.
The Standard Gates
| Gate | Transistors | Function | Key Property |
|---|---|---|---|
| NOT | 2 (1P + 1N) | Output = NOT A | Inverter — simplest gate |
| NAND | 4 (2P + 2N) | Output = NOT(A AND B) | Universal gate |
| NOR | 4 (2P + 2N) | Output = NOT(A OR B) | Universal gate |
| AND | 6 (NAND + NOT) | Output = A AND B | NAND followed by inverter |
| OR | 6 (NOR + NOT) | Output = A OR B | NOR followed by inverter |
| XOR | 8-12 | Output = A XOR B | Parity / difference detector |
How NAND is built: Two PMOS in parallel (pull-up) and two NMOS in series (pull-down). If either input is 0, a PMOS conducts and pulls output HIGH. Only when both inputs are 1 do both NMOS conduct, pulling output LOW.
How NOR is built: Two PMOS in series (pull-up) and two NMOS in parallel (pull-down). Only when both inputs are 0 do both PMOS conduct. If either input is 1, an NMOS conducts and pulls output LOW.
NAND as a Universal Gate
A remarkable property: any Boolean function can be built using only NAND gates. This is why NAND is called a "universal gate." The same is true for NOR. In practice, chip designers prefer NAND because NMOS transistors are faster than PMOS (electrons have higher mobility than holes), and NAND's pull-down network uses series NMOS — the speed-critical path.
- NOT from NAND: connect both inputs together — NAND(A, A) = NOT A
- AND from NAND: NAND followed by NOT — NAND(NAND(A, B), NAND(A, B))
- OR from NAND: NOT each input, then NAND — NAND(NAND(A, A), NAND(B, B))
Fan-In and Fan-Out
Fan-in is the number of inputs to a gate. A 2-input NAND has fan-in = 2. Increasing fan-in (e.g., 4-input NAND) adds more series transistors, which slows the gate because each transistor adds resistance.
Fan-out is the number of gate inputs that a single output drives. Higher fan-out means more capacitive load, which slows the driving gate's transition. Practical designs limit fan-out to 4-8 and insert buffers (two inverters in series) when driving many loads.
Propagation Delay
Every gate has a small propagation delay — the time for the output to respond after an input changes. Typical values in modern processes are 5-50 picoseconds per gate. The total delay through a chain of gates (the critical path) determines the maximum clock frequency of the circuit.
Real-Life: Building Any Circuit from NAND
Imagine you have a factory that produces only one type of brick — the NAND brick. Surprisingly, you can build any structure (AND wall, OR arch, XOR tower) using only this one brick type, just by combining them in different patterns.
This is exactly what happens in chip fabrication. Foundries optimize their manufacturing process for NAND gates because:
- NAND is the fastest gate (series NMOS in the critical pull-down path)
- Standardizing on one gate type simplifies manufacturing and testing
- Any arbitrary logic function can be decomposed into NAND-only form
In real hardware design:
- Standard cell libraries provide pre-characterized NAND, NOR, and other gates at various drive strengths. The synthesis tool maps your design to these cells.
- FPGAs use lookup tables (LUTs) — small truth-table memories — instead of discrete gates. A 4-input LUT can implement any function of 4 variables.
- Gate-level simulation is used to verify timing: does the signal arrive at every flip-flop input before the clock edge? Fan-in and fan-out directly affect these timing calculations.